***********
* Fragment PORT2.ASM (6811)
*
* This fragment permits use of second I/O cable as a parallel
* I/O port to interface with the I/O Box and other fixtures requiring
* and 8-bit input and output.
*
* Use: JSR INPORT2 - reads 8-inputs and returns the result in A.
*      JSR OUPORT2 - outputs the A accum to 8-outputs.
*
* Note that in using this arrangement there is no provision for
* bit setting and clearing.
*
* Note that these subroutines use labels;
* PORTA, PORTD, PORTE, DDRD, SPCR, SCCR2 and PACTL.  These labels
* may not be used in the calling program.
*
* Note that data is passed via acc A.  No variables are required.
*
* Note that the code is placed at PSCT+100 (normally $C100) and one 
* is reserved at DSCT+50 (normally $D050).  The user must have defined
* PSCT and DSCT in the calling program and avoid overlapping code and data.
* Note that a long jump (JSR) will normally be required.
*
* Problem.  There is a hardware problem.  If BIT0 on Cable 2 is at
* logic one, you may not be able to reset the processor.  Temporarily
* remove the cable or bring BIT0 to a logic zero.  We do not know why
* problem is occuring.
*
* To use with a program;
*
* AS11 file1.asm file2.asm port2.asm -l > file1.lst
*
*
* See PULSE_2 for an example of the operation.
*
* P. H. Anderson, Oct 16, 90, Checked.
***********

	ORG PSCT+$100

OUTPORT2
* outputs data in A to 8-bit parallel port on Cable #2

PORTA   EQU $00
PORTD   EQU $08
DDRD    EQU $09
SPCR    EQU $28
SCCR2   EQU $2D
PACTL   EQU $26


        PSHY            * save Y on stack
        PSHA            * save A on stack
        LDY #$1000      * register base
        BSET DDRD,Y %00001111   * config lo nibble as outputs
        BSET SPCR,Y %00100000   * set DWOM to one for PD0 bit
        BCLR SCCR2,Y %00001100  * disable Tx and Rx for PD1 and PD0
        BSET PACTL,Y %10000000  * config PA7 as output
        ANDA #$0F       * low byte isolated
        STAA PORTD,Y    * and output
        PULA            * get value again
        PSHA
        ANDA #$F0       * isolate high byte
        STAA PORTA,Y
        PULA
        PULY
        RTS

INPORT2
* inputs from 8-bit parallel port on Cable #2 and returns in A
* PORTA, PORTD, DDRD defined in OUTPORT2

PORTE   EQU $0A

        PSHY
        PSHB
        LDY #$1000
        LDAA PORTE,Y
        ANDA #$0F
        STAA TEMP_1
        LDAA PORTA,Y
        ANDA #$07
        ASLA
        ASLA
        ASLA
        ASLA
        ORAA TEMP_1
        ANDA #$7F
        STAA TEMP_1
        BCLR DDRD,Y %00100000
        LDAA PORTD,Y
        ASLA
        ASLA
        ANDA #$80
        ORAA TEMP_1
        PULB
        PULY
        RTS

	ORG DSCT+$50

TEMP_1  RMB 1