**********
* Program LOGIC_3 (6811)
*
* Simulates 8 bit shift register; parallel to serial converter.
*
* Fetches switches to load shift register.
* Successively outputs bits to LED #0 beginning with most
* significant bit.  Then repeats.
*
* P. H. Anderson, MSU, 11 Oct 90; 15 Jan 93
**********

PSCT	EQU  $C000
DSCT	EQU  $D000
IDSCT	EQU  $D300

STACKTP 	EQU  $0045
REG_BASE	EQU  $1000

PORTB	EQU  $04	* output
PORTC	EQU  $03	* input
DDRC	EQU  $07

	ORG PSCT

	LDS #STACKTP

	LDY #REG_BASE

	CLR DDRC,Y	* port c configured as 8-bit input
	CLR PORTB,Y	* zero the output

TOP
	LDAA PORTC,Y	* get switches, load shift register
	STAA SHIFT_REG

	LDAA #$08	* initialize bits to shift
	STAA BITS_LEFT
L1
	BSR SHIFT	* shift left and output ms bit
	DEC BITS_LEFT	* repeat until all bits shifted
	BNE L1
	BRA TOP 	* reload


SHIFT
* subroutine shift - shifts SHIFT_REG to left, outputs ms bit
* and provides time delay.

	PSHA		* save A on stack

	ASL SHIFT_REG	* shift to left, ms bit now in CY
	BCC OUT_0	* if CY zero, output $00
	BRA OUT_1	* otherwise output $01

OUT_0
	CLR PORTB,Y	* ls bit of output to zero
	BSR TIME	* brief delay

	PULA		* restore A
	RTS

OUT_1
	LDAA #$01	* ls bit of output to one
	STAA PORTB,Y
	BSR TIME

	PULA
	RTS

TIME
* subroutine time provides a nominal 0.25 sec delay

	PSHX		* save X on stack

	LDX #50000
DECR
	DEX
	BNE DECR

	PULX		* restore X
	RTS

	ORG DSCT

SHIFT_REG	RMB 1
BITS_LEFT	RMB 1